Fault-Aware Dual-Layer Adaptive Error Control Technique for NoC

Abstract

The network-on-a-chip (NoC) appeared as a promising solution to handle the communications requirements of the multiprocessor system-on-a-chip (MPSoC). As the complexity of designs rises and the technology scales down into the deep-submicron domain, the probability of errors in the NoC components increases. Fault tolerance is a vital aspect in designing NoC architectures for future MPSoCs. This paper proposes an adaptive fault-tolerant technique that is a hybrid end-to-end and hop-to-hop, offering benefits of both error control schemes, and introduces a fault-aware adaptive selective hop-to-hop error correction scheme. The proposed technique ensures improvement in reliability by reducing the latency of the network in low transient–noise conditions.