Abstract
Field experiences have demonstrated that semiconductor devices are vulnerable to failures, which challenges the reliability of power conversion systems. One of the most effective methods to enhance system reliability is fault-tolerant techniques. Presently, the parallel redundant converter approach is considered as one of the most effective fault-tolerant methods. However, there are some issues regarding parallel converter systems, such as surge currents that nonfaulty converters experience after faults, fault-isolation time, and load voltage distortion. To address these issues, this paper investigates the fault analysis and fault-tolerant design regarding parallel inverter systems. The stage analysis for the parallel inverter systems in the case of insulated-gate bipolar transistor short-circuit failures is performed first. Then, the surge current and the corresponding fault-isolation duration are explored. Furthermore, a mathematical model is built to address these two issues, and a fault-tolerant design to suppress surge current is presented. Finally, the experimental results are provided.
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