Fat Tree NoC Design and Synthesis

Abstract

Network on chip (NoC) architecture is the promising solution over the limitations of bus-based system. The on-chip communication is addressed by several NoC topological structures and guarantees reliable, fast, and scalable design. The paper addresses the design of fat NoC tree topology that can process the intercommunication from top to root nodes. The tree NoC is indirect topology in which the routers are not dependent on the number of ports. The design is developed in Xilinx ISE 14.2 software with the help of VHDL language, and the design is targeted on Virtex-5 FPGA. The hardware parameters and timing values are estimated to support the functionality of the design.