Abstract

The implementation of FASTBUS has required the parallel development of test modules peculiar to this bus system for debugging and testing. The complexity and speed of FASTBUS requires a new level of sophistication in these test modules. A good example of this is the Active Extender Card. The Crate Backplane of a FASTBUS system, which uses ECL 10K logic, has edge speeds high enough to require transmission lines. This means that a conventional extender card, such as is used in CAMAC, would act as an unterminated stub and cause significant reflections on the bus. Thus an extender has to be ''active'' and contain drivers and receivers for the bus. Some of the complexity is caused by the FASTBUS protocols. Although these protocols support an extremely flexible system architecture, a price must be paid with higher chip counts and wiring densities. I have attempted to give a brief description of the principle test modules that are used at Fermilab. More detailed information may be obtained in the references.

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