Fast Way-Prediction Instruction Cache for Energy Efficiency and High Performance

Abstract

This paper introduces a new way-prediction scheme for achieving low energy consumption and high performance for set-associative instruction cache. The proposed scheme is based on the different cases of how program execution proceeds. By predicting for the sequential instruction flow and non-sequential one respectively, we can achieve a high way prediction hit rate. Since way-prediction doesnpsilat increase the cache access time, we call it fast way-prediction cache (FWPC). Then we implement FWPC for instruction cache on GS232 processor. The experimental results came from FPGA shows that it has very high way prediction hit rate, which is 97.932% on average. The energy dissipation of instruction cache is reduced by 64.83% compared to conventional cache at the cost of 0.2% performance penalty, in which the way prediction miss only cost 0.38% power.