Fast VLSI architecture for rank order based filtering using a bit-serial window partitioning technique

Abstract

Based on a recently proposed algorithm for stack filtering, the bit-serial window partitioning (BSWP) algorithm, a new architecture suitable for the VLSI implementation of very fast rank order based filters for signal and image processing, is developed. The proposed architecture provides important improvements in terms of the running time (i.e., of the order of 30%-40%) compared to the conventional bit-serial binary tree search configuration for stack filtering, at the expense of only slightly increased chip area. The improved computational efficiency is obtained by evaluating the Boolean function at thresholds corresponding to the sample-values within the filter-window, and by taking advantage of the ordering information associated with the threshold sequences.