Fast test generation and partial testing for combinational logic circuits

Abstract

A simple, yet effective fast test generation algorithm by using the real value boolean difference is given for combinational logic circuits along with a short review of several fast test generation algorithms. Because no recursive operation is involved, it can be carried out as a parallel algorithm. In the second part of this paper, the concept of the partial testing is discussed. A new partial testing method, weighted point testing, is presented in this paper. Every line or node in the combinational logic circuit has a weight assigned to it. The weight at a point is determined by several factors, such as the fault occurrence found by experience or prior-knowledges, the number of fan-in or fan-out at that point, and the depth of the point in the circuit. Only those points with relatively high weights are considered in the test generation and testing. Because testing is more effectively done and directed to the point, the test coverage is higher.