Fast response 2-D rank order filter by using max-min sorting network

Abstract

Based on the sorting networks, a new VLSI architecture suitable for 2-D rank order filtering is proposed. The major advantage of the proposed architecture is the fast response time and modular architecture. Generally speaking, the throughput of the proposed architecture is (N-1) times faster than using a 1-D rank order filter for 2D N/spl times/N data. The concept of block processing is also incorporated into the design to reduce the time-area complexity of the proposed architecture. Roughly speaking, the complexity is reduced to 2/3 and 1/2 compared with a rank order and median filter without using block processing architecture, respectively. A 3/spl times/3 median filter with block processing architecture is implemented through a 0.8 /spl mu/m single-poly double metal CMOS process. The simulation results are correct with a clock rate up to 91 MHz.