Fast RC Reduction of Flip-Chip Power Grids Using Geometric Templates

Abstract

Realizable power grid reduction becomes a key to efficient design and verification of nowadays large-scale power delivery networks. Existing state-of-the-art realizable reduction techniques for interconnect circuits, such as the TICER algorithm, cannot be well suited for effective power grid reductions, since reducing the mesh-structured power grids by TICER's nodal elimination scheme may introduce excessive number of new edges in the reduced grids that can be even harder to solve than the original grid due to the drastically increased sparse matrix density. In this paper, we present a novel geometric template-based reduction technique for reducing large-scale flip-chip power grids. Our method first creates geometric template according to the original power grid topology and then performs novel iterative grid corrections to improve the accuracy by matching the electrical behaviors of the reduced template grid with the original grid. In addition, a multilevel grid correction scheme has been proposed to achieve faster convergence during the grid reduction process, which allows for effectively handling very large-scale power grids with millions of parasitics components and thousands of ports. Our experimental results show that the proposed reduction method can reduce industrial power grid designs by up to 95% with a very satisfactory solution quality obtained in dc and transient analysis.