Fast push at polysilicon deposition to reduce intrapoly oxide

Abstract

The polysilicon process had a problem with 15% higher average class probe sheet resistance on wafers running in the top furnace position at gate polysilicon and receive 'sandwich' polysilicon (thin poly deposition followed by gate poly deposition), than wafers that run in center and bottom of the furnace. The higher sheet resistance is caused by a thicker intrapoly oxide that grows between the thin polysilicon and the gate polysilicon on wafers in the top furnace position. By increasing the push speed from 25 minutes to 5 minutes and increasing the N2 purge during push, the intrapoly oxide was minimized and the class probe polysilicon sheet resistance distribution was tightened by over 50%. The fast push process also tightened the linear N-channel threshold voltage distribution by approximately 10%.© (1997) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.