Abstract
Genetic algorithm (GA) has been widely used since it was proposed. However, due to the complexity of the algorithm itself, the fact that the actual problems have huge data and scale, and that it needs to meet certain real-time requirements, the acceleration of genetic algorithm has become a hot spot in both academia and industry field. Previous work have been done on the acceleration of GA, which primarily focuses on the software aspect, while the existing work in hardware aspect lacks adaptability for different industrial scenarios. Therefore, this paper puts forward a novel architecture based on software/hardware co-design method, in which the software produces random numbers, and the hardware, taking full account of the characteristics of sequential circuit, is implemented in a hierarchical pipeline architecture. This architecture accelerates the algorithm while providing certain flexibility. This paper completes the simulation on MATLAB and Vivado, and the total running time is 987.4.u. Compared with the pure software implementation, the speed is increased by 73.9 times.
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