Abstract
In this paper, a fast FDTD solver is developed to perform the layout extraction and analysis of integrated circuits. In this solver, the time step is not restricted by the small space step encountered in the IC layout. Instead, it can be chosen to be arbitrarily large, thus making the full-wave FDTD simulation from DC to high frequencies become feasible. Meanwhile, the computational cost at each time step is also minimized via analytical identifications of the column space that determines the field solution. Numerical experiments have validated its accuracy and efficiency.
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