Fast extraction of predictive models for integrated circuits using n-performance Pareto fronts

Abstract

Predictive models based on Pareto fronts are key tools to understand and leverage tradeoffs in electronic circuit and system design. However, their generation conventionally requires the extensive use of numerical simulation and multi-objective optimization methods, resulting in significant computational cost. This cost increases exponentially with the number of parameters, and visualization also becomes an issue as the number of performance metrics increases. In this paper, we present a method to extract predictive models efficiently for electronic subsystems based on Pareto fronts. We use a very fast design and migration software called ID-Xplore™ to generate the performance space of sub-blocks in order to generate Pareto fronts for any block, thereby circumventing the traditional use of numerical optimization and thus accelerating the generation of Pareto-fronts for n-performance. We also combine the Pareto fronts in order to obtain one single Pareto front that represents all specifications, and use the Hyper-Space Diagonal Counting (HSDC) methodology to visualize n-performance Pareto fronts and combine the overall approach to help the designer in the final choice of optimal design points in the design of a state of the art OTA.