Fast division algorithm and its architecture over GF(2m)

Abstract

In this paper, a hardware algorithm is first proposed for executing fast division over GF(2 m ), and then an iterative GF divider is also designed based on the algorithm. The algorithm is based on the existing Extended binary GCD algorithm using standard basis representation. However, the proposed method decreases the operation time by using only two 1-bit flags for comparing the magnitude of S and R while the existing methods use m-bit comparator. From implementation results, the proposed scheme is shown to achieve the best performance in both area and speed aspects over the existing some algorithms. The designed 163-bit iterative divider is described using Verilog HDL, and it operates at a clock frequency of about 359 MHz on Xilinx FPGA with Virtex4-xc4vlx15 target device.