Fast Architecture for Low Level Vision and Image Enhancement for Reconfigurable Platform

Abstract

Image Processing architecture and algorithms are used for the purpose of improving the image quality and to extract complete information in more precise manner. The need to process in real time has led to implement them on the target device with real time constraints like power and area. To implement image processing algorithms and architecture with the help of high level languages needs more blocks of code apart from inefficient in terms of time constraint. The easiest way to deal with facilitating usage of Xilinx System Generator/XSG blocks, XSG is a tool where we can build our design using pre existing block level components which are captured by using Xilinx block set from library environment and implement as per user requirement. The main responsibility of system generator is Xilinx block sets that provides the package integration with MATLAB Simulink and helps in co- simulating FPGA hardware module. As per part application category, edge detection is a major essential application in medical field for proper diagnosis and correct treatments. Field-Programmable Gate Arrays (FPGAs) have become more popular computing platforms as target device for digital signal processing. The Zynq System on Chip (SOC) is a dual-processor platform with shared memory. This paper describes a fast architecture implementation of Sobel edge detection using the Zynq as a reconfigurable device. Our implementation is to merge both software and hardware using the Vivado and Zynq (SoC). As a result, our implementation is fast in terms of performance compare to the pre existing models. We make a comparison with other conventional edge detection techniques and show that the speed of operation of this design is much faster. This approach is tested over hardware or different gradient test vectors. Finally the algorithms are evaluated for the major essential images from the medical field to extract lasting effect in detecting the edges using gradient factor. The area and power factors are evaluated for reconfigurable hardware i.e, Zynq FPGA.