Fast and energy-efficient FPGA realization of RNS reverse converter for the ternary 3-moduli set {3n–2, 3n–1, 3n}

Abstract

Ternary number representation has been known as one of the efficient methods for the implementation of digital systems. Employing residue number system (RNS) in ternary digital signal processing (DSP) applications could offer the advantages of ternary number representation along with further privileges such as improving parallelism and fault tolerance. Efficacious design of reverse converter as a crucial block of residue number system has always been of great interest to researchers. In this paper, an efficient reverse converter for ternary RNS with moduli set {3n–2, 3n–1, 3n}, based on the mixed-radix conversion (MRC) algorithm is presented. The proposed algorithm reduces the number of adders with large bit-width and the dependencies between consecutively process blocks. The employed technique in the proposed algorithm and the reverse converter architecture improves the delay and area on the FPGA Virtex Ultrascale + family platform in 14 nm/16 nm FinFET technology as compared to the related works.