Fast and Accurate Code Placement of Embedded Software for Hybrid On-Chip Memory Architecture

Abstract

On chip SRAMs including scratchpad memories (SPMs) and caches are widely used in embedded systems to narrow the speed gap between CPU and memory. Memory subsystem acts as both performance and energy bottleneck for many applications in many contemporary embedded systems. While many off-the-shelf embedded processors employ the architecture with hybrid caches and SPMs on-chip memories, many existing work on SPM management ignore the synergy between caches and SPMs. In this work, we propose static SPM allocation strategy for the above-mentioned system architecture with the objective of minimizing the overall instruction memory subsystem latency and/or energy consumption. We capture the cache conflict misses with a fine-grained temporal cache behavior model. We propose an approximate knapsack based heuristic algorithm to generate an outstanding function-level SPM allocation which favors fast design space exploration. Compared with the state-of-the-art SPM heuristic allocation strategy, experimental results show that our SPM management scheme achieves 14.00% further improvement in instruction memory subsystem performance, and up to 17.69% in terms of energy saving.