Fast algorithm for HEVC intra‐coding implemented by preprocessing

Abstract

Compared to previous video compression standards H.264/AVC, high-efficiency video coding (HEVC) introduces a recursive quad-tree structure in intra-coding and adds intra-mode from 9 to 35 to achieve higher coding efficiency. The update significantly improves the performance of intra-coding. However, it greatly increases the amount of computation, and this will increase the need for the fast algorithm and hardware design that can satisfy the real-time encoding of HEVC encoder. In this study, the authors propose a fast intra-coding algorithm based on analysis of original pixel gradient texture. The algorithm consists of two steps, fast coding unit size decision and reduction of candidate modes. The experimental results show that compared with the HM16.7 encoder, the optimisation algorithm can obtain 50.7% time reduction on average with 1.32% Bjontegaard distortion (BD)-rate increase and 0.07 dB BD-peak-signal-to-noise ratio loss. Meanwhile, this study designs a pre-processing hardware structure based on original pixels. With TSMC 90 nm complementary metal oxide semiconductor technology, the proposed structure can achieve 625 MHz working frequency at the cost of 2094 gates, which can fulfil the throughput requirement of 8K × 4K@46 fps real-time encoding.