FAPS-3D

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Modern multiprocessor systems with multiple applications running concurrently lead to random memory access patterns during different phases of execution. Traditional static memory page policies used to exploit locality and minimize the access latency are not optimal under these varying memory access patterns. It requires a dynamic page management scheme to cope with these random memory access sequences to minimize memory access latency while maximizing available bandwidth utilization. The emergence of 3D-stacked DRAM provides several architectural advantages such as hundreds of memory banks to boost memory-level parallelism and availability of logic area to integrate custom logic in DRAM module. This paper introduces an adaptive page management scheme for 3D-stacked DRAM based main memory systems, which aims to minimize memory access latency by dynamically adjusting page modes based on the changing memory access patterns across different banks. The simulation results indicate that our scheme improves performance by 15.2% over the base close-page mode and by 4.0% over an existing access-based page management policy on average when running multi-programming SPEC workloads of varying memory intensities. It also outperforms a state-of-the-art time-based page management policy by 3.3%. Our scheme is implemented in the logic base of 3D-stacked DRAM module and has negligible area and energy overheads.