Abstract

Application requirements along with the unceasing demand for ever-higher scale of device integration, has driven technology towards an aggressive downscaling of transistor dimensions. This development is confronted with variability challenges, mainly the growing susceptibility to time-zero and time-dependent variations. To model such threats and estimate their impact on a system's operation, the reliability community has focused largely on Monte Carlo-based simulations and methodologies. When assessing yield and failure probability metrics, an essential part of the process is to accurately capture the lower tail of a distribution. Nevertheless, the incapability of widely-used Monte Carlo techniques to achieve such a task has been identified and recently, state-of-the-art methodologies focusing on a Most Probable Failure Point (MPFP) approach have been presented. However, to strictly prove the correctness of such approaches and utilize them on large scale, an examination of the concavity of the space under study is essential. To this end, this paper develops an MPFP methodology to estimate the failure probability of a FinFET-based SRAM cell, studying the concavity of the Static Noise Margin (SNM) while comparing the results against a Monte Carlo methodology.

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