Abstract
Knowledge of the electrical failure modes and of the physical mechanisms that cause faults is fundamental to implementing realistic fault models. Therefore, failure physics is the basis of effectual test sequence generation, and can give guidelines also for the design of testable and reliable integrated circuits. In the paper the failure modes and mechanisms of complex integrated circuits are reviewed. Faults are classified with respect to their allocation in the devices. Bulk defects, and failures in the dielectric layers, metallisation and package interconnections are then examined. Special attention is devoted to failures spurred by the reduction of dimensions for VLSI ('scaling')
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