Failure Mechanisms and Testing in Nanometer Technologies

Abstract

CMOS technology scaling has been a constant since its initial development in the early 70’s as an effort to obtain ICs working at higher operating frequencies that perform more operations per unit area. Each advance in CMOS technology scaling is called a technology generation, or a technology node, and pursues the ability of fabricating smaller transistors. A new technology generation doubles the number of transistors per unit area, increases operating frequency by more than 40%, reduces the energy per transition by more than 60%, while reducing transistor cost. Technology nodes are reached at a constant pace, a rule known as Moore’s law, which currently brings one new generation every 18 months. Moore’s law is possible thanks to the scalability of the basic unit used to implement digital switches: the MOSFET transistor. Today ICs contain transistors having minimum geometries of 90 nm (1nm = 10 –9 m), and industry is now rapidly moving into the 65 nm technology node. Chips today contain hundreds of millions of transistors and operate at frequencies on the order of 5 GHz. They incorporate a variety of circuit blocks