Abstract
New wafer fabrication process integration uses copper metallization and low-k dielectric material to resolve the performance limitation of aluminum interconnect technology. The implementation of low-k BEOL dielectrics has weakened the die in terms of mechanical properties compared to non- low-k dielectrics, such as SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , BPSG, and TEOS. It has been experienced that during physical analysis of low-k devices, sample preparation plays an important and crucial part in ensuring that the evidence to the root cause is preserved and does not induce further damage to the samples that could lead the analysis to a different conclusion. This paper discusses the problems observed during analysis on packaged low-k dice, and possible solutions.
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