Failure analysis of ESD damage on interconnects in LCD GOA

Abstract

Liquid crystal display (LCD) is likely to accumulate charge and incur ESD events due to the insulating glass plate. In our study, an ESD induced failure of interconnects in LCD gate driver on array (GOA) was analyzed. The monochrome pattern test was conducted to locate the failure site. The morphology of the failure site was characterized by SEM, EDS and FIB. Charge accumulation on long interconnects in the VUV-cleaning process, and subsequent discharging damage at narrow interconnect gaps were analyzed to be the root cause of failure. Furthermore, some specimens were designed to validate the analysis, design of experiments was performed to study the effects of the gap space and the interconnect length on the failure severity. Based on the experimental data, a logistic model was developed to model the failure severity, which can help to provide suggestions for designs to reduce the incidence of failures.