Failure Analysis of Commercial Ferroelectric Random Access Memory for Single Event Effect

Abstract

In this article, the single event responses of a 4-Mb commercial two-transistor and two-capacitor (2T2C) ferroelectric random access memory (FRAM) are studied. A microbeam was used to identify sensitive circuit areas. Various response categories are identified. The two most vulnerable sensitive areas were investigated using reverse engineering, and the results indicate that the n-well resistors located in the peripheral circuits are the primary source of the bit upset response and functional interruption. Analysis results indicate that ion strikes on the n-well resistor generate current disturbances in circuits, which can alter the polarization state of the ferroelectric bit storage capacitor and interrupt the data transfer process of the device.