Fail mechanism of program disturbance for erase cells VT positive shift in NAND flash technology

Abstract

Program disturbance is a major intrinsic reliability concern on NAND flash. In this paper, we present that NAND flash E/W (Erase/Write) cycle failures induced by program disturbance for erase cells VT (Threshold Voltage) positive shift. The root cause of program disturbance is the old process of gate re-oxidation issue, which results in ILD (Intra-Layer Dielectric) voids, then Ni fills in the ILD voids and induces the lateral E-field increase between WL's. Interface traps and electrons generated by GIDL (Gate Induce Drain Leakage) are accelerated by the lateral E-field and subsequently injected into the erase cell transistors by HCI effect, therefore erase cells VT positive shift, and program disturbance occurs. The disturbance will get worse than fresh sample as interface traps and couple voltage of WLs increasing after E/W cycles. A new process of gate re-oxidation to depress the program disturbance and enhance NAND Flash E/W cycles performance is provided.