FaFNoC: A Fault-tolerant and Bufferless Network-on-chip

Abstract

Abstract Deflection routing is a promising approach for energy and hardware efficient NoCs. Future VLSI designs will have an increasing susceptibility to failures and breakdowns. The inherent redundancy of NoCs can be used to tolerate such failures. We extended the non-fault-tolerant CHIPPER router architecture to enable fault-tolerance. This architecture is based on deflection routing and utilizes a permutation network instead of a crossbar. Compared to a crossbar based design, a permutation network allows a faster and smaller router design. Simulations of a 8 × 8 network and more than 30.000 flit injections show, that our router architecture is competitive with existing crossbar based fault-tolerant router architectures.