Factors influencing the performance of InP metal/insulator/semiconductor field effect transistors

Abstract

It was demonstrated that the deposition process used to form the gate insulator of an InP metal/insulator/semiconductor field effect transistor (FET) is of fundamental importance in determining the level of device performance. In a comparative study of gate insulators, it was observed that devices incorporating Si 3N 4 exhibited virtually no enhanced conduction, whilst those with SiO 2 seemed to be limited to a channel mobility of around 1000 cm 2 V -1s -1. Both dielectrics were produced using a plasma-enhanced deposition technique, and these low mobilities are interpreted as being a consequence of plasma damage to the InP surface. In contrast a pyrolytically deposited Al 2O 3 dielectric resulted in devices with a mobility of up to 2000 cm 2 V -1s -1. Furthermore the presence of substrate defects was shown to be equally critical in determining device performance. Plasma damage to the substrate surface during the dielectric growth appears to be significantly reduced by high temperature annealing. This improvement was advantageously employed in the fabrication of ion-implanted self-aligned gate InP metal/oxide/semiconductor FETs incorporating a plasma-deposited SiO 2 gate insulator. These devices exhibited channel mobilities of up to 2400 cm 2 V -1s -1.