Abstract
AbstractThis paper describes a very high‐speed coding and decoding processor Image Pipeline Codec (ImPC, MN86063), which can be applied to bi‐level image, focusing on the architectural design and performance evaluations. An application example for a facsimile apparatus also is presented.The ImPC integrates basic functions required for an advanced facsimile such as two‐channel encoding and decoding, resolution conversion, and direct memory access (DMA) transfer functions. The ImPC includes the redundancy reduction coding algorithms modified Huffman (MH), modified READ (MR), modified MR (MMR), and an original coding scheme. A line of 4096 alternating black and white pixels can be encoded or decoded in 0.84 ms with 100‐ns cycle time. A typical A4 size office document is processed in 0.17 s. The ImPC chip is fabricated using 1.2 μ CMOS technology, integrating approximately 480,000 transistors on a 98‐mm2 die.
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