Fabrication of thin film transistors using a Si/Si/sub 1-x/Ge/sub x//Si triple layer film on a SiO2 substrate

Abstract

A novel approach that can reduce the thermal budget in the fabrication of thin film transistors (TFTs) using a Si/Si/sub 0.7/Ge/sub 0.3//Si triple film as an active layer was proposed. The crystallization behavior of the triple film was described and device characteristics of Si/Si/sub 0.7/Ge/sub 0.3//Si TFTs were compared with those of Si TFTs and of SiGe TFTs. The triple film was completely crystallized only after a 25-h anneal at 550/spl deg/C. N-channel polycrystalline Si/Si/sub 0.7/Ge/sub 0.3//Si TFTs had a field-effect mobility of 57.9 cm/sup 2//Vs and an I/sub on//I/sub off/ ratio of 5.7/spl times/10/sup 6/. This technique provides not only a shorter time processing capability than Si TFT's technology but also superior device characteristics compared to SiGe TFTs.