Fabrication of thickness-controlled silicon nanowires and their characteristics

Abstract

A process for fabricating thin Si nanowires is proposed which can reduce the parasitic series resistance of the nanowire. The process includes electron cyclotron resonance plasma deposition of a SiO2 film through the openings of a patterned resist film. Since the SiO2 thickness decreases as the opening narrows, the SiO2 film can be made thinnest in the nanowire region. Therefore, during the following reactive-ion etching, the SiO2 film in this region is removed first and the Si layer is then selectively etched. A Si nanowire fabricated through this process shows quantized conductance at temperatures as high as 200 K.