Fabrication of silicon on lattice-engineered substrate (SOLES) as a platform for monolithic integration of CMOS and optoelectronic devices

Abstract

We report the fabrication of a novel substrate platform for the monolithic integration of Si-based CMOS and GaAs-based optoelectronic devices. This platform, which we refer to as silicon on lattice-engineered substrate (SOLES), consists of a compositionally graded Si 1− x Ge x buffer buried underneath an SOI structure, all fabricated on a Si substrate. The Si 1− x Ge x graded buffer was grown by UHVCVD and was capped with a Ge-rich alloy that is closely lattice-matched to GaAs (0.96 < x Ge < 1) and provides a threading dislocation density (TDD) of ∼10 6 cm −2. While these Si 1− x Ge x graded buffers have been proven by previous studies to be an effective platform for fabrication of GaAs-based LEDs, lasers, and solar cells on Si substrates, the integration of both Si- and GaAs-based devices on a single chip using this technique is hampered by the large thickness (∼10 μm) of the Si 1− x Ge x graded buffer. SOLES eliminates this drawback by the addition of the SOI structure on top of the Ge-rich cap. This approach provides for a Si device layer in close proximity to the GaAs-based device layer, thereby simplifying the monolithic integration of Si- and GaAs-based devices with this platform. Fabrication consists of layer transfer of Si to an oxide-coated graded buffer using oxide–oxide wafer bonding followed by hydrogen-induced layer exfoliation of the Si layer from its donor wafer. Our results show this layer transfer occurs reliably across the entire wafer, making it amenable to commercial application.