Fabrication of lateral resonant tunneling devices with heterostructure barriers

Abstract

Lateral resonant tunneling devices that employ heterostructure charge barriers are candidates to replace complementary metal–oxide–semiconductor devices as the basic device type that will drive integrated circuit technology in the next century. We present progress in lateral resonant tunneling device technology including the first lateral resonant tunneling transistor that has heterostructure barriers to be fabricated with planar processing techniques. The devices produced to date are limited to cryogenic operation; however, they do demonstrate that lateral resonant tunneling devices can be fabricated with etch and regrowth techniques and suggest the possibility of an integrated circuit technology that may be scaled down to less than 10 nm and would operate at room temperature.