Fabrication of gated nanosize Si-tip arrays for high perveance electron beam applications

Abstract

Nanosize Si-tip arrays with gated electrodes have been fabricated using the self-aligned method. In order to have a parallel electron beam (high perveance beam) toward the anode plate, we have designed a nanosize tip array with heights of the tip slightly less than that of a gate electrode. A high perveance beam is supposed to provide better focusing of the electron beams. Hence, it is important to have a high perveance electron beam for nanolithographic application. The fabricated procedures for nanoscale Si-tip array are reactive ion etching, sharpening, and oxidation followed by a 7:1 BHF oxide etch. The metal gate fabrication procedures are performed with self-aligned techniques using plasma oxide deposition, metal sputter deposition, and photoresist spin coating. The self-aligned methods allow for a controlling gate aperture less than 1.0 μm. The structure of the fabricated gated electron source was designed to have a 1.5 μm gate aperture, a 1.5 μm SiO2 insulating layer, and a 0.3 μm Mo volcano-type gate electrode. The Fowler–Nordheim and current–voltage characteristics of the fabricated tip arrays after seasoning the tip in a high vacuum chamber (<5×10−8 Torr) were examined carefully and its turn-on voltage was found to be ∼25 V. The observed bright electron spots on the anode screen was measured to be ∼300 μA. The total area for the (300×300) Si-tip array was ∼1.5 mm2. A charge coupled device camera photographed the bright area on the anode phosphor plate from electron bombardments and the size of electron bombardment spot was almost the same as the original tip array area (1.8 mm2). In addition, we have also fabricated the gated Si-tip arrays with a focusing electrode for angular confinement of the electron beam emission and high perveance for the beam trajectory.