Fabrication, Characterization, and Simulation of a Low-Cost TSV Integration Without Front-Side CMP Process

Abstract

In this paper, a low-cost through-multilayer TSV integration process has been developed. The features are that a double-layer spin coating technique is applied to prevent residual photoresist left inside TSVs. Besides, redistribution layer is deposited before TSV filling in order to eliminate the front-side chemical-mechanical planarization process, which will lower the fabrication cost. Basic electrical tests of single layer chip are performed in order to pick out these known good dies for stacking. A given mass of stacking TSV integration samples are fabricated. Electrical test results are presented to show the quality of TSV interconnects and TSV isolation. The quality of bonding strength is characterized through shear tests, and the optimized bonding parameters are put forward after a set of experiments with different parameter combinations. The mean of bonding precision is $3.31~{\mu }\text{m}$ , with the bonding yield being 94.17%. Thermodynamic simulation is simulated to characterize the stress and warping values of this multi-layers TSV integration. All test results support the good quality of this through-multilayer integration approach.