Fabrication and Characterization of SiGe on Insulator through Condensation and Wafer Bonding Techniques

Abstract

SiGe on insulator (SGOI) is desired to obtain microelectronic devices with high performance and low leakage current. The manufacturing of silicon on insulator (SOI) has been already developed and the wafers are on the market with different expenses and qualities. Nevertheless the fabrication techniques of SGOI is more complex than SOI wafers. In this study two different techniques has been applied to fabricate SGOI wafers. The advantages and disadvantages of both techniques have been discussed in details and the wafers have been characterized in terms of defect density, roughness, uniformity and fabrication process parameters. The original wafers for condensation technique were SOI with 50 nm Si top and 400 nm buried oxide. The 100 nm Si0.74Ge0.26 was epitaxially grown on SOI wafers followed by 10 nm Si cap layer using chemical vapor deposition (CVD) technique. The Si cap/ Si0.74Ge0.26/ Si structure went through condensation where Si cap layer oxidize immediately and Si0.74Ge0.26/Si was sandwiched between two oxide layers. The consequence of Ge diffusion to the beneath Si layer result single layer Si0.53Ge0.47on insulator (SGOI). In the wafer bonding technique as second method, Si0.53Ge0.47 has grown epitaxially on a Si wafer. The direct bonding applied between donor and acceptor wafers. The bonded wafers are then annealed in order to strength the bonding. The etch-back process begins by thinning down the donor wafer to leave the Si0.53Ge0.47 on insulator. The quality and electrical transport of condensed and bonded SiGe layer were examined using high resolution reciprocal lattice mapping (HRRLM), scanning electron microscopy (SEM), Rutherford back scattering (RBS), atomic force microscopy (AFM), hall measurement technique in van der pauw structure and four probe measurement technique. The results show the condensation layer undergo defects which originate from condensation process compared to bonding layer which possess lower defect density. This study will help to continue optimizing of substrate engineering of group IV alloys for implementation on next silicon technology.