Abstract
A 1 k-bit 1T2C-type ferroelectric memory cell array has been designed and fabricated by combination of a 0.35 µm design rule for the complementary metal-oxide-semiconductor (CMOS) process and a 3 µm design rule for the ferroelectric and interconnection processes. Basic operations such as random access writing and readout operations, nondestructive data readout for more than 104 readout pulses, data retention for 10 days, and data disturbance characteristics for more than 104 unipolar pulses have been demonstrated in the fabricated 1T2C-type cell array.
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