Fabrication and characteristics of Germanium-On-Insulator substrates

Abstract

The fabrication of Germanium-On-Insulator (GeOI) by wafer bonding and ion-cut approach was investigated. With cyclic HF/DIW cleaning and N2 plasma surface activation, large-area layer transfer of GeOI substrates was realized by ion-cut processes with bulk Ge wafer as the donor wafer. The GeOI substrates are thermally stable up to 550°C annealing and surface roughness can be smoothed down to 0.3 nm RMS by Chemical Mechanical Planarization (CMP). After surface polishing, Epi-Ge on Si wafer can also be used as the donor wafer to realize layer transfer. Four-probe configuration Pseudo-MOSFET was employed to characterize the electrical properties of the transferred Ge and the Ge/SiO2 bonding interface. At Ge/SiO2 interface, GeOI substrates show both accumulation and inversion conduction modes. High-temperature forming gas annealing in the vicinity of 500°C?600°C has shown the best carrier mobilities, with the interface trap density and interface fixed charge density as low as 1010/cm2. The extracted bulk hole mobility of the annealed GeOI is near 500 cm2/V-s, which is higher than that of silicon (300 cm2/V-s) at the same doping concentration level.