Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI)

Abstract

A through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration is reviewed. Polymer-based Cu-RDL interconnects provide a CMP less low-cost fabrication alternative enabling outsourced semiconductor assembly and test (OSATs) to fabricate and assemble a 2.5-D low-cost through silicon interposer (LC-TSI) in low-cost infrastructure facilities. Standard TSV processing involving etch, isolate, seed layer deposition, and Cu-fill is employed. First, TSVs are etched using standard BOSCH etch, followed by isolation using subatmospheric chemical vapor deposition (SACVD) process and TaN barrier seed deposition and end up with the Cu electroplating (ECP) and CMP. At the first step, SiO 2 passivation is performed followed by the Ti/Cu seed layer sputtering as step 2. In step 3, photoresist (PR) is spin coated and soft baked followed by the exposure and development of PR in step 4. Comparing the manufacturing costs of Cu-damascene as well as Cu-RDL technologies, it is expected that adapting Cu-RDL technology should effectively reduce the 2.5-D TSI manufacturing cost by 20% based on our cost model. The manufacturing cost is expected to reduce further by 10%-12% when the lithography exposure wavelength is changed from i-line lithography to GHI-line lithography.