Abstract
A simulation-based analysis of extremely scaled double-gate (DG) CMOS, emphasizing the effects of gate-induced drain leakage (GIDL) in DG MOSFETs, is described. Device and ring-oscillator simulations project an enormous performance potential for DG/CMOS, but also show how and why GIDL can be much more detrimental to off-state current in DG devices than in the single-gate counterparts. However, for asymmetrical (n/sup +/ and p/sup +/ polysilicon) gates, the analysis further shows that the GIDL effect can be controlled by tailoring the back (p/sup +/-gate) oxide thickness, which implies design optimization regarding speed as well as static power in DG/CMOS circuits.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
