Extremely high simulated ballistic currents in triple-heterojunction tunnel transistors

Abstract

Future VLSI devices will require low CV dd 2/2 switching energy, large on-currents (I on ), and small off-currents (I off ). Low switching energy requires a low supply voltage V dd , yet reducing V dd typically increases /off and reduces the I on /I off ratio. Though tunnel FETs (TFETs) have steep subthreshold swings and can operate at a low V dd , yet their I on is limited by low tunneling probability. Even with a GaSb/InAs heterojunction (HJ), given a 2nm-thick-channel (001)-confined TFET, [100] transport, and assuming V dd =0.3V and I oFF =10−3A/m, the peak tunneling probability is on is only 24 A/m (fig. 1b) [1]. This low I on will result in large CV dd /I delay and slow logic operation. Techniques to increase /on include graded AlSb/AlGaSb source HJs [2,3] and tunneling resonant states [4]. We had previously shown that tunneling probability is increased using (11 0) confinement and channel heterojunctions [1], the latter increasing the junction built-in potential and junction field, hence reducing the tunneling distance. Here we propose a triple heterojunction TFET combining these techniques. The triple-HJ design further thins the tunnel barrier to 1.2 nm, and creates two closely aligned resonant states 57meV apart. The tunneling probability is very high, >50% over a 120meV range, and the ballistic I on is extremely high, 800A/m at 30nm Lg and 475 A/m at 15nm Lg, both with I off =10−3 A/m and V dd =0.3 V. Compared to a (001) GaSb/InAs TFET, the triple-HJ design increases the ballistic /on by 26:1 at 30nm L g and 19:1 at 15nm L g . The designs may, however, suffer from increased phonon-assisted tunneling.