Extraction of the Lateral Position of Border Traps in Nanoscale MOSFETs

Abstract

A novel method for the extraction of the lateral position of border traps in nanoscale MOSFETs is presented. Using technology computer-aided design (TCAD) simulations, we demonstrate that the dependence of the trap-induced threshold voltage shift on the drain bias is more sensitive to the lateral trap position than to the impact of random dopants. Based on this, the lateral defect position can be determined with a precision of several percent of the channel length. To demonstrate the correct functionality of our technique, we apply it to extract the lateral positions of experimentally observed traps. Although the most accurate algorithm is based on time-consuming TCAD simulations, we propose a simplified analytic expression, which allows for the extraction of the lateral trap position directly from the experimental data. While the uncertainty introduced by random dopants is <10% for the TCAD model, the additional errors introduced by the simple analytic expression still provide trap positions accurate to 5% for the devices with 20-nm channel length and 20%–25% for 100-nm-long devices.