Extraction of DC-Biased SFQ Circuit Verilog Models

Abstract

The increase in complexity of superconducting single flux quantum circuits enabled by the IARPA Cryogenic Computing Complexity project has highlighted the need for hardware description language (HDL) models that allow fast and reliable simulation and verification of such circuits. The design of new cell libraries for successive nodes of fabrication processes also exposed the cost of building new HDL models for each cell library. We expand an automatic HDL extraction method presented earlier to provide a fully automated tool for timing model extraction from an arbitrary cell the functionality of which does not need to be known. We describe in detail how models for the Verilog HDLs are constructed to allow timing verification and to implement delays as functions of bias, process tolerances, thermal noise, and load. Modeling of wire length delays is discussed, and results presented for complex circuits synthesized with new place-and-route algorithms.