Extensive Analysis on the Effects of Post-Deposition Annealing for ALD-Deposited Al2O3 on an n-Type Silicon Substrate.

Atish Bhattacharjee,Tae-Woo Kim

doi:10.3390/ma14123328

Abstract

In this study, an investigation was performed on the properties of atomic-layer-deposited aluminum oxide (Al2O3) on an n-type silicon (n-Si) substrate based on the effect of post-deposition heat treatment, which was speckled according to ambient temperature and treatment applied time. Based on these dealings, a series of distinctions for extracted capacitance and dielectric constant, hysteresis was performed on annealed and nonannealed samples. The interface and border trap responses, including stress behavior after an application of constant voltage for a specific time and surface morphology by X-ray diffraction (XRD) technique, were also analyzed between the two above-mentioned sample types. Based on observation, the annealed samples showed superior performance in every aspect compared with the nonannealed ones. Some unusual behaviors after high annealing temperature were found, and the explanation is the ion diffusion from oxide layer towards the semiconductor. Since a constant voltage stress was not widely used on the metal–oxide–semiconductor capacitor (MOSCAP), this analysis was determined to reveal a new dimension of post-deposition annealing condition for the Al/Al2O3/n-Si gate stack.

Highlights

A large band gap and an exalted barrier height between the dielectric and Si has essential chemical, along with the thermal steadiness of the conventional dielectric material silicon dioxide (SiO2 ), on silicon (Si) wafers [1,2,3]
The leakage current and equivalent oxide thickness (EOT), which are associated with the speed of the transistor, can be decreased with a denser oxide layer with a high dielectric constant (k)
The metal–oxide– semiconductor capacitor (MOSCAP) annealed at 300 ◦ C for 5 min has the highest capacitance, and the 500 ◦ C–5 min sample has the lowest

Summary

Introduction

A large band gap and an exalted barrier height between the dielectric and Si has essential chemical, along with the thermal steadiness of the conventional dielectric material silicon dioxide (SiO2 ), on silicon (Si) wafers [1,2,3]. The combination of the precursor/oxidant pulses and purge gas flow is acknowledged as a half cycle; the film is deposited through this self-saturating half cycle because the reactions stop once all reactive components on the Si surface are devoured. Throughout this process, the reactions are eradicated by themselves [9]. The self-saturating nature and cyclic deposition deliver amenable, disciplined, uniform, high-quality, condensed, and pinhole-free thin films with thickness errors of less than 1%; the film growth is autonomous of the precursor and oxidant flux [7,10].

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Results

Conclusion