Extension and very large scale integration implementation of the majority-gate algorithm for gray-scale morphological operations

Abstract

This paper presents the design and VLSI implementation of a new ASIC that performs in real time the morphological operations of dilation and erosion. The ASIC’s architecture is based on the extension of the majority-gate algorithm for morphological operations. The ASIC was implemented using a DLM, 0.7-?m, CMOS, N-well process, and it occupies a silicon area of 14.78 mm2. Its maximum speed of operation is 92.5 MHz. Targeted applications include machine vision, where the need for short processing times is crucial.