Abstract

The recent technology roadmap suggests a continuous trend of miniaturizing the pattern size in the upcoming generation. Double patterning technology is already in practical use for 32 nm HP patterning for memory device production. EUVL may be in need for 2x nm HP and beyond. However, it is facing challenges such as insufficient source power, mask defects and resist. EUVL development is supposed to delay due to those remaining technical obstacles. In that case, double patterning technology will be most likely the solution to accommodate 2x nm HP and beyond.

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