Exposing ILP in custom hardware with a dataflow compiler IR

Abstract

With the impending Dark Silicon problem spelling doom for multicore performance scaling, there is an ever increasing need for processor architectures with much better energy efficiency. To address this, designers are increasingly utilising custom (and reconfigurable) computing to provide orders-of-magnitude improvements in energy efficiency over equivalent software implementations of the same code. Unfortunately, one of the key issues with custom computing is that it is often unable to match the performance of conventional processors when implementing irregular code with complex control-flow. Out-of-order superscalar processors implement aggressive branch prediction to speculate across multiple branches with very high accuracy, dynamically exposing ILP. But custom hardware lacks an efficient and safe control-flow speculation mechanism (particularly for loops), as it is difficult to implement misprediction roll-back and recovery in hardware without introducing a centralized synchronization bottleneck. By providing a mechanism for compiling high level languages to hardware, as well as improving performance of control-flow intensive code in hardware, much more pervasive utilization of custom and reconfigurable hardware were enable for general-purpose computation, thereby helping to mitigate the effects of dark silicon.