Exploring design tradeoffs in analog IC placement with current-flow & current-density considerations

Abstract

In this paper, the concept of hierarchical multi-objective optimization (MOO) is applied to analog integrated circuit (IC) placement automation, where current-flow and current-density considerations are taken to improve the reliability and, reduce the routing-induced parasitics of the circuit post-layout. The current-flow constraints are satisfied by forcing a monotonic routing directly in an absolute placement representation, while the impact of current-intensive interconnects is mitigated with the electromigration (EM)-aware optimization of the wiring topology (WT) for all nets of the circuit. The problem's complexity is reduced using the hierarchy in the circuit's partitions, combining, bottom-up, Pareto optimal fronts (POFs) of placements that explore the tradeoffs between the design objectives. The approach is demonstrated with post-layout results in an analog circuit structure for the UMC 130nm design process.