Abstract
Testing different modules of an integrated circuit concurrently is an efficient way to reduce the total test time. This paper presents a procedure to optimize the parallel test plan to test all functional units present in a data path. Our algorithm defines which registers will be transformed into test pattern generators (TPGs) and signature analyzers SAs, minimizing a test cost function. Our procedure assumes that cellular automata (CAs) registers will be used both for TPG and SA. Each FU's test is defined in terms of: registers to be used as TPGs; registers to be used as SAs; CAs rules to implement TPG and SA; number of test vectors; fault coverage; and test session. Very good results were obtained for the tested architectures. A comparison between the parallel test and a serial test has shown a large test time reduction with a small hardware penalty. This procedure is part of an ongoing research which consists of the development of tools to automatically generate BIST testable circuits along with complete optimized test plans for architectures synthesized by the MACH High-Level Synthesis System.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
