Exploring CMOS logic families in sub-threshold region for ultra low power applications

Abstract

Numerous efforts in balancing the trade-off between power, area and performance have been done in the medium performance, medium power region of the design spectrum. However, not much study has been done at the two extreme ends of the design spectrum, namely the ultra-low power with acceptable performance at one end and high performance with power within limit at the other. One solution to achieve the ultra-low power requirement is to operate the digital logic gates in sub-threshold region. In this paper, we investigate different logic families in sub-threshold region for ultra-low-power applications. For the first time, the performance characteristics of inverter and also the basic gates for different logic families operating in the sub- threshold region have been compared using 90nm technology cadence circuit simulations. The results of the simulations show that the sub-threshold logics have some advantages compared to their strong inversion counterparts. Enhancing the performance of these circuits will leads to enhancement of overall system performance.